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陈普峰

作品数:6 被引量:2H指数:1
供职机构:中国科学院微电子研究所更多>>
发文基金:国家重点基础研究发展计划国家自然科学基金更多>>
相关领域:电子电信更多>>

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4~8GHz GaAs HBT单片双平衡混频器
2008年
介绍了一种基于GaAs HBT的双平衡混频器。该混频器将射频、本振有源Balun集成其中,在RF和LO输入端分别采用不同的LC网络实现宽带的阻抗匹配。跨导级和开关单元之间采用交流耦合,并通过带宽扩展技术实现频带内的增益平坦。测量结果显示,该混频器匹配良好,射频端口S11在3~10GHz频带内小于-10dB。在固定中频200MHz情况下测试,在4~8GHz射频频带内,平均增益10dB,波动小于1dB,中频输出端口对射频信号的隔离度优于25dB,对本振信号的隔离度优于28dB;本振-射频端口隔离度优于32dB。在3.3V直流电压下测得的功耗为66mW。
张健张海英陈立强李志强陈普峰
关键词:GAASHBT混频器带宽扩展
C波段宽带GaAs HBT单片双平衡混频器
介绍了一种基于GaAs HBT的双平衡混频器。该混频器将射频、本振有源Balun集成其中,在RF和LO输入端分别采用不同的LC网络实现宽带的阻抗匹配。跨导级和开关单元之间采用交流耦合,并通过带宽扩展技术实现频带内的增益平...
张健张海英陈立强李志强陈普峰
关键词:混频器阻抗匹配
0.5μm GaAs PHEMT数字衰减器设计被引量:1
2008年
采用0.5μm GaAs PHEMT工艺设计了两款工作于1~4 GHz的数字衰减器。一款为选择式衰减器,衰减量0.5 dB和15 dB,插入损耗≤1 dB,所有衰减状态的输入输出驻波比≤1.7;另外一款为3 bit数字衰减器,衰减步进0.8 dB,最大衰减量5.6 dB,插入损耗≤1 dB,所有衰减状态的输入输出驻波比≤1.8,相对于参考态,衰减态的插入相移在-3°-2°之间。
刘会东张海英孙肖磊陈普峰
关键词:微波单片集成电路宽带数字衰减器砷化镓赝配高电子迁移率晶体管
Design of a 2.5GHz Low Phase-Noise LC-VCO in 0.35μm SiGe BiCMOS
2008年
This paper introduces a 2.5GHz low phase-noise cross-coupled LC-VCO realized in 0.35μm SiGe BiCMOS technology. The conventional definition of a VCO operating regime is revised from a new perspective. Analysis shows the importance of inductance and bias current selection for oscillator phase noise optimization. Differences between CMOS and BJT VCO design strategy are then analyzed and the conclusions are summarized. In this implementation, bonding wires form the resonator to improve the phase noise performance. The VCO is then integrated with other components to form a PLL frequency synthesizer with a loop bandwidth of 30kHz. Measurement shows a phase noise of - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from a 2.5GHz carrier. At a supply voltage of 3V, the VCO core consumes 8mA. To our knowledge,this is the first differential cross-coupled VCO in SiGe BiCMOS technology in China.
张健陈立强李志强陈普峰张海英
关键词:VCOINDUCTANCE
An Improved Charge-Averaging Charge Pump for a Fractional-N Frequency Synthesizer
2008年
An improved charge-averaging charge pump and the corresponding circuit implementation are presented. The charge-averaging charge pump proposed by Koo is analyzed and a new scheme is proposed. This new scheme decreases power by 1/3 and eliminates the practical defects in the original. Spectre Verilog behavioral simulation results show that the proposed scheme can strongly reduce the energy of spurs. Circuit implementation of this new charge pump for a frequency synthesizer with a fractional division ratio of 1/3 is then presented and multi-level simulation is performed to validate its feasibility at the circuit level. The simulation results show this new scheme outputs a flat voltage curve in a locked state and can thus effectively suppress fraction spurs.
张健黄水龙李志强陈普峰张海英
关键词:SPUR
A High Purity Integer-N Frequency Synthesizer in 0.35μm SiGe BiCMOS被引量:1
2008年
An integer-N frequency synthesizer in 0.35μm SiGe BiCMOS is presented. By implementing different building blocks with different types of devices,a high purity frequency synthesizer with excellent spur and phase noise performance has been realized. All the building blocks are implemented with differential topology except for the off-chip loop filter. To further reduce the phase noise,bonding wires are used to form the resonator in the LC-VCO. The frequency synthesizer operates from 2.39 to 2.72GHz with output power of about 0dBm. The measured closed-loop phase noise is - 95dBc/Hz at 100kHz offset and - 116dBc/Hz at 1MHz offset from the carrier. The power level of the reference spur is less than - 72dBc. With a 3V power supply, the whole chip including the output buffers consumes 60mA.
张健李志强陈立强陈普峰张海英
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